Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are synthesis, placement, and routing of the system on the target device.
As technology progresses, the demand for higher data rate for communication components implemented on the target devices have increased to support video imaging, wireless communication, data storage, and other applications. With high-speed input/output (I/O) interface data rates doubling every few years, it has become necessary to accurately model transmitters, receivers, and interconnects between the transceivers and receivers on target devices to predict the quality of performance of high speed serial channels. Simulation tools offer designers the ability to model the characteristic of channels and evaluate their performance. Both transistor-level simulation methods and behavior-level simulation methods have been used.
When modeling the transmitters, receivers, and interconnects, it is important to take into account of any crosstalk which may adversely impact the integrity of the signals transmitted. In electronics, crosstalk is the phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit, part of a circuit, or channel, to another.